1. Field of the Invention
This invention relates generally to data processing systems and more particularly to data processing systems wherein individual central processing units include a temporary storage unit generally referred to as a cache memory.
2. Description of the Prior Art
A cache memory is a relatively small, high speed memory unit for temporary storage of information signals. The cache memory is generally implemented in such a manner that the information signals stored therein can be accessed by an associated central processing unit more rapidly than if the information signals were transferred directly from the main memory of a data processing system. Because of the more rapid information signal access capability by the central processing unit, information signals frequently used by the central processing unit are stored in the main memory unit and are duplicated in the cache memory thereby improving the performance of the central processing unit (hereafter referred to as the CPU).
Thus when the CPU requires selected groups of information signals, a directory, forming a portion of the cache memory and containing the equivalent of the main memory address of each valid group of information signals stored in cache memory, is first examined, and if the desired information signals are determined to be stored in cache memory, then the information signals are transferred from the cache memory unit to the central processor unit without accessing the main memory unit. If the selected groups of signals are not found in the cache memory unit, then the location containing those groups of signals are transferred from the main memory unit to the CPU. Depending on the strategy utilized in storing information signal groups in the cache memory, the information signals transferred to the CPU can be stored in the cache memory during the transfer from the main memory unit to the CPU.
Because a plurality of processors as well as a plurality of peripheral devices can have access to the main memory, the information signal groups currently in the main memory at a given location are subject to change and consequently the information signal groups in a cache memory unit, identified to the CPU only by an equivalent of the main memory location address, will no longer be an accurate reflection of the information signals actually at that main memory location. To avoid inconsistencies that can arise when different sets of data are identified as equivalent (i.e. the address of the main memory location where the signals are stored), the data currently stored in the main memory location is assumed to be the correct data. Information signals in the cache memory that have main memory location addresses in which the signal groups have been independently altered must be rendered unavailable to the associated CPU of the data processing system.
The operation which can accomplish this purpose is a cache memory clearing operation wherein the contents of all the cache memories are made unavailable to the CPUs whenever an operation changing data in the main memory unit is identified. However, this process is clearly inefficient because valid data and invalid data in the cache memory units are rendered unavailable to the CPUs indiscriminately.
Many data processing systems utilize segmentation and paging techniques when manipulating data in the main memory. Segments (or portions) of the main memory refer to groups of information signals having some selected relationship. The main memory segments are further divided pages which are groups of information signals (i.e. of the related segment of a predetermined dimension). Thus, in the cache memory unit that stores information signals by page address, when the information signals of a selected page address can be changed by operation involving the main memory, the related information signal having that selected page address stored in the cache memory units are rendered unavailable to the CPUs. Again, this type of invalidation or clearing of the cache memory signal groups is inefficient because of insufficient granularity of the cache memory storage location clearing mechanism.
It is also possible to provide directories that duplicate the actual directory location in the cache memory unit. The data processing system can, when specified activities are performed in the main memory, examine a duplicate directory and determine if the information signal groups stored in the related cache memory storage location can be affected by the main memory operation. In the event that the validity of the contents of the cache memory is comprised, then the contents of the actual cache memory storage location, in response to signals from the related duplicate directory, are altered so that the information signals compromised by the main memory operation are no longer available to the affected CPUs of the data processing system. This method of insuring accuracy of the cache memory contents requires a large amount of additional apparatus.